HD6432351 Datasheet, PDF (570/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Bit Rate
(bit/s)
ø = 2 MHz ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz
n
N
n
N
n
N
n
N
n
N
n
N
110
3
70 — —
250
2
124 2
249 3
124 — — 3
249
500
1
249 2
124 2
249 — — 3
124 — —
1k
1
124 1
249 2
124 — — 2
249 — —
2.5 k
0
199 1
99 1
199 1
249 2
99 2
124
5k
0
99 0
199 1
99 1
124 1
199 1
249
10 k
0
49 0
99 0
199 0
249 1
99 1
124
25 k
0
19 0
39 0
79 0
99 0
159 0
199
50 k
0
9
0
19 0
39 0
49 0
79 0
99
100 k
0
4
0
9
0
19 0
24 0
39 0
49
250 k
0
1
0
3
0
7
0
9
0
15 0
19
500 k
0
0* 0
1
0
3
0
4
0
7
0
9
1M
0
0* 0
1
——0
3
0
4
2.5 M
——0
0* — — 0
1
5M
——0
0*
Note: As far as possible, the setting should be made so that the error is no more than 1%.
Legend
Blank : Cannot be set.
— : Can be set, but there will be a degree of error.
* : Continuous transfer is not possible.
550