HD6432351 Datasheet, PDF (23/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 1-1 Overview (cont)
Item
Data transfer
controller (DTC)
16-bit timer-pulse
unit (TPU)
Programmable
pulse generator
(PPG)
Watchdog timer
Serial communica-
tion interface (SCI)
2 channels
A/D converter
D/A converter
I/O ports
Memory
Specification
• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
• 6-channel 16-bit timer on-chip
• Pulse I/O processing capability for up to 16 pins'
• Automatic 2-phase encoder count capability
• Maximum 16-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or inverse output setting possible
• Watchdog timer or interval timer selectable
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function
• Resolution: 10 bits
• Input: 8 channels
• High-speed conversion : 6.7 µs minimum conversion time
(at 20 MHz operation)
• Single or scan mode selectable
• Sample and hold circuit
• A/D conversion can be activated by external trigger or timer trigger
• Resolution: 8 bits
• Output: 2 channels
• 87 I/O pins, 8 input-only pins
• Mask ROM
• High-speed static RAM
Product Name
H8S/2350
H8S/2351
ROM
—
64 kbytes
RAM
2 kbytes
2 kbytes
Interrupt controller • Nine external interrupt pins (NMI, IRQ0 to IRQ7)
• 42 internal interrupt sources
• Eight priority levels settable
3