HD6432351 Datasheet, PDF (155/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access
to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the
RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode).
RAS down mode cannot be used with the 2-CAS method. When selecting RAS down mode, set
the BE bit to 1.
Bit 5
RCDM
0
1
Description
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
(Initial value)
Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit
DRAM space, and 0 otherwise.
Bit 4
CW2
0
1
Description
16-bit DRAM space selected
8-bit DRAM space selected
(Initial value)
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