HD6432351 Datasheet, PDF (571/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

The BRR setting is found from the following formulas.
Asynchronous mode:
N=
ø
× 10⁶ – 1
64 × 2^2n–1 × B
Clocked synchronous mode:
N=
ø
× 10⁶ – 1
8 × 2^2n–1 × B
Where B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
ø: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
1
ø/4
0
1
2
ø/16
1
0
3
ø/64
1
1
The bit rate error in asynchronous mode is found from the following formula:
Error (%) = {
ø × 10⁶
(N + 1) × B × 64 × 2^2n–1
– 1} × 100
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