HD6432351 Datasheet, PDF (180/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.5 DRAM Interface
6.5.1 Overview
When the H8S/2350 Series is in advanced mode, external space areas 2 to 5 can be designated as
DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be
directly connected to the H8S/2350 Series. A DRAM space of 2, 4, or 8 Mbytes can be set by
means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode.
6.5.2 Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas
(areas 2 to 5).
Table 6-5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces
RMTS2
0
RMTS1
0
1
RMTS0
1
0
1
Area 5
Normal space
Normal space
DRAM space
Area 4
Area 3
Area 2
DRAM space
DRAM space
6.5.3 Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6
shows the relation between the settings of MXC1 and MXC0 and the shift size.
Table 6-6 Address Multiplexing Settings by Bits MXC1 and MXC0
MCR _Shift
MXC1 MXC0 Size
Address Pins
A₂₃ to A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
Row 0
0
8 bits
A₂₃ to A₁₃ A₂₀ A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈
address
1
9 bits
A₂₃ to A₁₃ A₁₂ A₂₀ A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ A₉
1
0
10 bits A₂₃ to A₁₃ A₁₂ A₁₁ A₂₀ A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀
1 Setting —
prohibited
—————————————
Column — — —
address
A₂₃ to A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
160