HD6432351 Datasheet, PDF (80/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

End of bus request
Bus request
End of bus
request
Bus-released state
Program execution
state
Bus
request
SLEEP
instruction
with
SLEEP _{SSBY = 0}
instruction
with
SSBY = 1
End of
exception
handling
Request for
exception
handling
Sleep mode
Exception-handling state
Interrupt
request
External interrupt
Software standby mode
RES = high
Reset state^*1
STBY = high, RES = low
Hardware standby mode^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2-15 State Transitions
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The
CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the
NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when
the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,
Watchdog Timer.
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