HD6432351 Datasheet, PDF (857/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Full address mode (cont)
Bit
:7
6
5
4
DMACRB : —
DAID DAIDE —
Initial value : 0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
Data Transfer Factor
DTF DTF DTF DTF
3 210
0 000 —
Block Transfer Mode
Normal Mode
—
1 ^{Activated by A/D converter conversion} —
end interrupt
1
0
Activated by DREQ pin falling edge input
Activated by DREQ
pin falling edge input
1 Activated by DREQ pin low-level input
Activated by DREQ
pin low-level input
1
0
0
Activated by SCI channel 0 transmission
complete interrupt
—
1
Activated by SCI channel 0 reception
complete interrupt
—
1
0
Activated by SCI channel 1 transmission
complete interrupt
Auto-request (cycle
steal)
1
Activated by SCI channel 1 reception
complete interrupt
Auto-request (burst)
1
0
0
0
Activated by TPU channel 0 compare
match/input capture A interrupt
—
1
Activated by TPU channel 1 compare
match/input capture A interrupt
—
1
0
Activated by TPU channel 2 compare
match/input capture A interrupt
—
1
Activated by TPU channel 3 compare
match/input capture A interrupt
—
1
0
0
Activated by TPU channel 4 compare
match/input capture A interrupt
—
1
Activated by TPU channel 5 compare
match/input capture A interrupt
—
10—
—
1—
—
Destination Address Increment/Decrement
0 0 MARB is fixed
1 MARB is incremented after a data transfer
1 0 MARB is fixed
1 MARB is decremented after a data transfer
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