HD6432351 Datasheet, PDF (247/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

7.5 Operation
7.5.1 Transfer Modes
Table 7-5 lists the DMAC modes.
Table 7-5 DMAC Transfer Modes
Transfer Mode
Transfer Source
Remarks
Short
address
mode
Dual (1) Sequential mode _{• TPU channel 0 to 5} • Up to 4 channels can
address
mode
(2) Idle mode
(3) Repeat mode
compare match/input
operate independently
capture A interrupt _{• External request}
• SCI transmission
applies to channel B
complete interrupt
only
• SCI reception complete• Single address mode
interrupt
applies to channel B
• A/D converter
only
conversion end
• Modes (1), (2), and (3)
interrupt
can also be specified
• External request
for single address
mode
(4) Single address mode
Full address
mode
(5) Normal mode
(6) Block transfer
mode
• External request
• Max. 2-channel
• Auto-request
operation, combining
channels A and B
• TPU channel 0 to 5 • ^{With auto-request,}
compare match/input
burst mode transfer or
capture A interrupt
cycle steal transfer can
• SCI transmission
be selected
complete interrupt
• SCI reception complete
interrupt
• A/D converter
conversion end
interrupt
• External request
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