HD6432351 Datasheet, PDF (865/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF35
DTC
Bit
:
Initial value :
Read/Write :
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
DTC Activation Enable
DTC activation by this interrupt is disabled
0 [Clearing conditions]
• When the DISEL bit is 1 and data transfer has ended
•When the specified number of transfers have ended
DTC activation by this interrupt is enabled
1 ^{[Holding condition]}
When the DISEL bit is 0 and the specified number of
transfers have not ended
Correspondence between Interrupt Sources and DTCER
Register
DTCERA
DTCERB
DTCERC
DTCERD
DTCERE
DTCERF
Bits
7
6
5
4
3
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
—
ADI
TGI0A
TGI0B
TGI0C
TGI2A
TGI2B
TGI3A
TGI3B
TGI3C
—
—
TGI5A
TGI5B
—
DMTEND0A DMTEND0B DMTEND1A DMTEND1B RXI0
—
—
—
—
—
2
IRQ5
TGI0D
TGI3D
—
TXI0
—
1
IRQ6
TGI1A
TGI4A
—
RXI1
—
0
IRQ7
TGI1B
TGI4B
—
TXI1
—
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