HD6432351 Datasheet, PDF (619/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial
Status Register (SSR).
However, the setting conditions for the TEND bit, are as shown below.
Bit 2
TEND
Description
0
[Clearing conditions]
(Initial value)
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
1
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character when GM = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
14.2.3 Serial Mode Register (SMR)
Bit
:
7
GM
Initial value :
0
Set value* : GM
R/W
: R/W
6
5
CHR
PE
0
0
0
1
R/W
R/W
4
3
O/E STOP
0
0
O/E
1
R/W
R/W
2
MP
0
0
R/W
1
CKS1
0
CKS1
R/W
0
CKS0
0
CKS0
R/W
Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6,
5, 3, and 2.
The function of bit 7 of SMR changes in smart card interface mode.
Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set
to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced
and clock output control mode addition is performed. The contents of the clock output control
mode addition are specified by bits 1 and 0 of the serial control register (SCR).
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