HD6432351 Datasheet, PDF (505/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 10-55 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Buffer register write cycle
T1
T2
Buffer register
address
N
M
N
M
Figure 10-55 Contention between Buffer Register Write and Input Capture
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