HD6432351 Datasheet, PDF (168/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D₁₅ to D₈) and lower data bus (D₇ to D₀) are used
for accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword transfer instruction is executed as two word transfer instructions.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Byte size
Byte size
• Even address
• Odd address
Upper data bus
Lower data bus
D₁₅
D₈ D₇
D₀
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6-5 Access Sizes and Data Alignment Control (16-Bit Access Space)
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