HD6432351 Datasheet, PDF (446/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.2.4 Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit
:
7
6
TTGE
—
Initial value :
0
1
R/W
: R/W
—
5
4
3
2
1
0
— TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit
:
Initial value :
R/W
:
7
TTGE
0
R/W
6
5
4
3
— TCIEU TCIEV —
1
0
0
0
—
R/W R/W
—
2
1
0
— TGIEB TGIEA
0
0
0
—
R/W R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
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