HD6432351 Datasheet, PDF (981/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table D-2 I/O Port States in Each Processing State (H8S/2350) (cont)
MCU
Port Name Operating
Pin Name Mode
Power-
On
Manual
Reset Reset
Hardware Software
Standby Standby
Mode Mode
Bus
Release
State
PG₀/CAS 1 to 3, 7
T
kept
T
kept
kept
4 to 6
T
[DRAME = 0] T
kept
[DRAME = 1]
H*
[DRAME = 0] T
kept
[OPE = 0]
T
[DRAME ·
OPE= 1]
CAS
Legend:
H
: High level
L
: Low level
T
: High impedance
kept
: Input port becomes high-impedance, output port retains state
DDR
: Data direction register
OPE
: Output port enable
WAITE : Wait input enable
BRLE : Bus release enable
BREQOE : BREQO pin enable
DRAME : DRAM space setting
LCASE: DRAM space setting, CW2 = LCASS = 0
Note: * Indicates the state after completion of the executing bus cycle.
Program
Execution
State
Sleep Mode
I/O port
[DRAME = 0]
Input port
[DRAME = 1]
CAS
961