HD6432351 Datasheet, PDF (501/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 10-51 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
TCNT
TGR
TGR write cycle
T1
T2
TGR address
N
N
TGR write data
Inhibited
N+1
M
Figure 10-51 Contention between TGR Write and Compare Match
481