HD6432351 Datasheet, PDF (531/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

11.3.5 Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 11-7.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
95
65
59
56
95
65
PODRL
00
95 05 65 41 59 50 56 14 95 05 65
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Time
Figure 11-8 Inverted Pulse Output (Example)
511