PXN20RM Datasheet, PDF (994/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
If the eSCI module is in SCI mode and the system stop signal is asserted and no transmission or reception
is running, the eSCI module enters the halt mode.
31.1.3.4.2 Leaving Halt Mode into SCI Mode
If the eSCI module is in halt mode and the system stop signal is de-asserted and the LIN bit and the MDIS
bit are 0, the eSCI module enters the SCI mode. The TRDE flag is set. No data will be transmitted as long
as new data is provided by the application. If the receiver is still enabled, it starts the detection of the start
bit.
31.1.3.4.3 Entering Halt Mode from LIN Mode
If the eSCI module is in LIN mode and the system stop signal is asserted while a LIN byte field or character
transmission is running, the eSCI module performs a shut down of the transmit process. Therefore, it
continues the ongoing LIN byte field or character transmission until the last bit of the LIN byte field or
character has been transmitted. After the end of the transmission, all pending transfer requests are cleared
and no more data will be transmitted. None of the transmitter related register flags will be set.
If the eSCI module is in LIN mode and the system stop signal is asserted while a LIN byte field or character
reception is running, the eSCI module aborts the reception immediately. None of the receiver related
register flags will be set.
If the eSCI module is in LIN mode and the system stop signal is asserted and no transmission or reception
is running, the eSCI module resets the LIN protocol engine to its idle state, resets the write access counter
of the LIN Transmit Register (eSCI_LTR) and enters the halt mode.
31.1.3.4.4 Leaving Halt Mode into LIN Mode
If the eSCI module is in halt mode and the system stop signal is de-asserted and the LIN bit is set and the
MDIS bit is 0, the eSCI module enters the LIN mode. The TXRDY flag is set. No data will be transmitted
as long as new LIN frame header data is provided by the application. If the receiver is still enabled, it starts
the detection of the start bit.
31.2 External Signal Description
Each eSCI_x module has two external signals: TXD_x (transmit data output of eSCI_x) and RXD_x
(receive data input of eSCI_x). Refer to Table 3-1 and Section 3.4, Detailed Signal Description, for
detailed signal descriptions.
31.3 Memory Map and Registers
This section provides the memory map and a detailed description of the memory mapped registers.
31.3.1 Memory Map
The eSCI memory map is shown in Table 31-1. The address of each register is given as an offset to the
eSCI base address. Registers are listed in address order, identified by complete name and mnemonic, and
include the type of accesses allowed.
31-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor