PXN20RM Datasheet, PDF (233/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x0C44
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PC0:PC15
W
Reset U U U U U U U U U U U U U U U U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PD0:PD15
W
Reset U U U U U U U U U U U U U U U U
Figure 8-41. Parallel GPIO Pin Data Input Register 1 (SIU_PGPDI1)
8.3.2.34 Parallel GPIO Pin Data Input Register 2 (SIU_PGPDI2)
Reads to the SIU_PGPDI2 register provide the parallel GPIO pin data input for PE0:PE15 and PF0:PF15.
Writes have no effect.
Reads of this register are coherent with the registers SIU_GPDI64_67, SIU_GPDI68_71,
SIU_GPDI72_75, SIU_GPDI76_79, SIU_GPDI80_83, SIU_GPDI84_87, SIU_GPDI88_91, and
SIU_GPDI92_95.
Offset: SIU_BASE + 0x0C48
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PE0:PE15
W
Reset U U U U U U U U U U U U U U U U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PF0:PF15
W
Reset U U U U U U U U U U U U U U U U
Figure 8-42. Parallel GPIO Pin Data Input Register 2 (SIU_PGPDI2)
8.3.2.35 Parallel GPIO Pin Data Input Register 3 (SIU_PGPDI3)
Reads to the SIU_PGPDI2 register provide the parallel GPIO pin data input for PG0:PG15 and PH0:PH15.
Writes have no effect.
Reads of this register are coherent with the registers SIU_GPDI96_99, SIU_GPDI100_103,
SIU_GPDI104_107, SIU_GPDI108_111, SIU_GPDI112_115, SIU_GPDI116_119, SIU_GPDI120_123,
and SIU_GPDI124_127.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-51