PXN20RM Datasheet, PDF (448/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Protection Unit (MPU)
Table 18-5. MPU_EDRn Field Descriptions
Field
Description
EACD
Error Access Control Detail. This 16-bit read-only field implements one bit per region descriptor and is an indication
of the region descriptor hit logically-ANDed with the access error indication. The MPU performs a
reference-by-reference evaluation to determine the presence/absence of an access error. When an error is detected,
the hit-qualified access control vector is captured in this field.
If the MPU_EDRn register contains a captured error and the EACD field is all zeroes, this signals an access that did
not hit in any region descriptor. All non-zero EACD values signal references that hit in a region descriptor(s), but failed
due to a protection error as defined by the specific set bits.
EPID Error Process Identification. This 8-bit read-only field records the process identifier of the faulting reference. The
process identifier is typically driven by processor cores only; for other bus masters, this field is cleared.
EMN Error Master Number. This 4-bit read-only field records the logical master number of the faulting reference. This field
is used to determine the bus master that generated the access error.
EATTR
Error Attributes. This 3-bit read-only field records attribute information about the faulting reference. The supported
encodings are defined as:
000 User mode, instruction access.
001 User mode, data access.
010 Supervisor mode, instruction access.
011 Supervisor mode, data access.
All other encodings are reserved. For non-core bus masters, the access attribute information is typically wired to
supervisor, data (0b011).
ERW
Error Read/Write. This 1-bit read-only field signals the access type (read, write) of the faulting reference.
0 Read.
1 Write.
18.3.2.4 MPU Region Descriptor n (MPU_RGDn)
Each 128-bit (16 byte) region descriptor specifies a given memory space and the access attributes
associated with that space. The descriptor definition is fundamental to the operation of the MPU.
The region descriptors are organized sequentially in the MPU’s programming model and each of the four
32-bit words are detailed in the subsequent sections.
18.3.2.4.1 MPU Region Descriptor n, Word 0 (MPU_RGDn.Word0)
The first word of the MPU region descriptor defines the 0-modulo-32 byte start address of the memory
region. Writes to this word clear the region descriptor’s valid bit.
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PXN20 Microcontroller Reference Manual, Rev. 1
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