PXN20RM Datasheet, PDF (544/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Table 24-19. TCDn 32-bit Memory Structure (continued)
eDMA Offset
0x1000+(32 x n)+0x000C
0x1000+(32 x n)+0x0010
0x1000+(32 x n)+0x0014
0x1000 (32 x n) 0x0018
0x1000+(32 x n)+0x001c
TCDn Field
Last source address adjustment (slast)
Destination address (daddr)
Current major iteration count (citer)
Signed destination address offset (doff)
Last destination address adjustment / scatter-gather address (dlast_sga)
Beginning major iteration count (biter)
Channel control/status
Figure 24-18 and Table 24-20 define the fields of the TCDn structure.
Word
Offset _{0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31}
0x0000
SADDR
0x0004
0x0008
SMOD
SSIZE
DMOD
DSIZE
NBYTES¹
SOFF
0x8
MLOFF or NBYTES ¹
NBYTES¹
0x000C
0x0010
SLAST
DADDR
0x0014
CITER or
CITER.LINKCH
CITER
DOFF
0x0018
DLAST_SGA
0x001C
BITER or
BITER.LINKCH
BITER
BWC MAJOR LINKCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 24-18. TCD Structure
1 _{The fields implemented in Word 2 depend on whether EDMA_CR(EMLM) is set to 0 or 1. Refer to Table 24-3.}
NOTE
The TCD structures for the eDMA channels shown in Figure 24-18 are
implemented in internal SRAM. These structures are not initialized at reset;
therefore, all channel TCD parameters must be initialized by the application
code before activating that channel.
24-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor