PXN20RM Datasheet, PDF (788/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Table 27-15. CBCR Field Descriptions
Field
Description
CRBA Control Receive Base Address. This base address is shared by all control RX channels and defines the upper 16
[31:16] bits of the 32-bit system memory address for these channels.
CTBA Control Transmit Base Address. This base address is shared by all control TX channels and defines the upper 16
[31:16] bits of the 32-bit system memory address for these channels.
27.3.2.9 Isochronous Base Address Configuration Register (IBCR)
The Isochronous Base Address Configuration Register (IBCR) allows system software to define the base
address for isochronous RX/TX system memory buffers.
Offset: MLB_BASE + 0x002C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
IRBA[31:16]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ITBA[31:16]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-10. Isochronous Base Address Configuration Register (IBCR)
Table 27-16. IBCR Field Descriptions
Field
Description
IRBA Isochronous Receive Base Address. This base address is shared by all Isochronous RX channels and defines the
[31:16] upper 16 bits of the 32-bit system memory address for these channels.
ITBA Isochronous Transmit Base Address. This base address is shared by all Isochronous TX channels and defines the
[31:16] upper 16 bits of the 32-bit system memory address for these channels.
27.3.2.10 Channel Interrupt Configuration Register (CICR)
The Channel Interrupt Configuration Register (CICR) reflects the channel interrupt status of the individual
MLB logical channels. These bits are set by hardware when a channel interrupt is generated. The channel
interrupt bits are sticky and can only be reset by software.
27-16
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor