PXN20RM Datasheet, PDF (201/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
8.3.2.7 Overrun Status Register (SIU_OSR)
The SIU_OSR contains flag bits that record an overrun. These flag bits are cleared by writing 1 to the bits
(w1c); writing 0 has no effect.
Offset: SIU_BASE + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R _OVF
W ¹⁵
Reset w1c
17
OVF
14
w1c
18
OVF
13
w1c
19
OVF
12
w1c
20
OVF
11
w1c
21
OVF
10
w1c
22
OVF
9
w1c
23
OVF
8
w1c
24
OVF
7
w1c
25
OVF
6
w1c
26
OVF
5
w1c
27
OVF
4
w1c
28
OVF
3
w1c
29
OVF
2
w1c
30
OVF
1
w1c
31
OVF
0
w1c
Figure 8-8. Overrun Status Register (SIU_OSR)
Table 8-10. SIU_OSR Field Descriptions
Field
Function
OVFn
Overrun Flag n. This bit is set when an overrun occurs on the corresponding IRQn pin.
0 No overrun occurred on the corresponding IRQn pin.
1 An overrun occurred on the corresponding IRQn pin.
8.3.2.8 Overrun Request Enable Register (SIU_ORER)
The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If
any overrun request enable bit and the corresponding flag bit are set, the single combined overrun request
from the SIU to the interrupt controller is asserted.
Offset: SIU_BASE + 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R _ORE
W ¹⁵
Reset 0
17
ORE
14
0
18
ORE
13
0
19
ORE
12
0
20
ORE
11
0
21
ORE
10
0
22
ORE
9
0
23
ORE
8
0
24
ORE
7
0
25
ORE
6
0
26
ORE
5
0
27
ORE
4
0
28
ORE
3
0
29
ORE
2
0
30
ORE
1
0
31
ORE
0
0
Figure 8-9. Overrun Request Enable Register (SIU_ORER)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-19