PXN20RM Datasheet, PDF (614/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Table 25-37. Transmit Buffer Descriptor Field Definitions
Halfword Location Field Name
Description
Offset + 0 Bit 0
R
Ready. Written by the FEC and the user.
0 The data buffer associated with this BD is not ready for transmission. The user is free
to manipulate this BD or its associated data buffer. The FEC clears this bit after the
buffer has been transmitted or after an error condition is encountered.
1 The data buffer, which has been prepared for transmission by the user, has not been
transmitted or is currently being transmitted. No fields of this BD may be written by the
user once this bit is set.
Offset + 0 Bit 1
TO1 Transmit software ownership. This field is reserved for software use. This read/write bit
is not modified by hardware, and its value does not affect hardware.
Offset + 0 Bit 2
W
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.
Offset + 0 Bit 3
TO2 Transmit software ownership. This field is reserved for use by software. This read/write
bit is not modified by hardware, and its value does not affect hardware.
Offset + 0 Bit 4
L
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Offset + 0 Bit 5
TC
Tx CRC. Written by user (only valid if L = 1).
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
Offset + 0 Bit 6
ABC
Append bad CRC. Written by user (only valid if L = 1).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value).
Offset + 0 Bits [7:15]
—
Reserved.
Offset + 2 Bits [0:15]
Offset + 4 Bits [0:15]
Data
Length
A[0:15]
Data length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s data buffer.
It is never modified by the FEC. Bits [0:10] are used by the DMA engine, bits[11:15] are
ignored.
Tx data buffer pointer, bits [0:15]¹
Offset + 6 Bits [0:15] A[16:31] Tx data buffer pointer, bits [16:31].
1 _{The transmit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 4. The}
buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
NOTE
Once the software driver has set up the buffers for a frame, it should set up
the corresponding BDs. The last step in setting up the BDs for a transmit
frame should be to set the R bit in the first BD for the frame. The driver
should follow that with a write to TDAR, which triggers the FEC to poll the
next BD in the ring.
25-48
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor