PXN20RM Datasheet, PDF (1241/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Table 36-60. Program Trace Exception Summary
Exception Condition
Exception Handling
System Reset Negation
At the negation of JTAG reset (JCOMP), queue pointers, counters, state machines, and
registers within the Nexus2+ module are reset. Upon the first branch out of system
reset (if program trace is enabled), the first program trace message is a direct/indirect
branch with sync. message.
Program Trace Enabled
The first program trace message (after program trace has been enabled) is a
synchronization message.
Exit from Low Power/Debug
Upon exit from a low power mode or debug mode, the next direct/indirect branch is
converted to a direct/indirect branch with sync. message.
Queue Overrun
An error message occurs when a new message cannot be queued due to the message
queue being full. The FIFO discards messages until it has completely emptied the
queue. Once emptied, an error message is queued. The error encoding indicates which
types of messages attempted to be queued while the FIFO was being emptied. The
next BTM message in the queue is a direct/indirect branch with sync. message.
Periodic Program Trace Sync.
A forced synchronization occurs periodically after 255 program trace messages have
been queued. A direct/indirect branch with sync. message is queued. The periodic
program trace message counter then resets.
Event In
If the Nexus module is enabled, an EVTI assertion initiates a direct/indirect branch with
sync. message upon the next direct/indirect branch (if program trace is enabled and the
EIC bits of the DC1 register have enabled this feature).
Sequential Instruction Count Overflow When the sequential instruction counter reaches its maximum count (as many as 255
sequential instructions may be executed), a forced synchronization occurs. The
sequential counter then resets. A program trace direct/indirect branch with
sync.message is queued upon execution of the next branch.
Attempted Access to Secure Memory For devices that implement security, any attempted branch to secure memory locations
temporarily disables program trace and causes the corresponding BTM to be lost. The
following direct/indirect branch queues a direct/indirect branch with sync. message. The
count value within this message is inaccurate since the re-enable of program trace is
not necessarily aligned on an instruction boundary.
Collision Priority
All messages have the following priority: WPM  OTM  BTM  DTM. A BTM
message that attempts to enter the queue at the same time as a watchpoint message
or ownership trace message is lost, and an error message is sent indicating the BTM
was lost. The following direct/indirect branch queues a direct/indirect branch with sync.
message. The count value within this message reflects the number of sequential
instructions executed after the last successful BTM Message was generated. This
count includes the branch that did not generate a message due to the collision.
36.7.9.3.3 BTM Operation
Enabling Program Trace
Both types of branch trace messaging are enabled using one of the following methods:
• Setting the TM field of the DC1 register to enable program trace (DC1[TM])
• Using the PTS field of the WT register to enable program trace on watchpoint hits (e200z0 watch
points are configured within the CPU)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-91