PXN20RM Datasheet, PDF (946/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Offset: DSPI_BASE + 0x0034
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CONT
W
CTAS
EOQ
CT
CNT
0
0
0
0
PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TXDATA
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-8. DSPI PUSH TX FIFO Register (DSPI_PUSHR)
Table 30-14. DSPI_PUSHR Field Descriptions
Field
Description
CONT
Continuous Peripheral Chip Select Enable. The CONT bit selects a Continuous Selection Format. The bit is used in
SPI master mode. The bit enables the selected PCS signals to remain asserted between transfers. See
Section 30.4.8.5, Continuous Selection Format, for more information.
Note: To ensure PCS stability during data transmission in Continuous Selection Format (and Continuous SCK clock
enabled) make sure that the data with reset CONT bit is written to DSPI_PUSHR register before previous data
sub-frame (with CONT bit set) transfer is over.
0 Return Peripheral Chip Select signals to their inactive state between transfers.
1 Keep Peripheral Chip Select signals asserted between transfers.
CTAS
Clock and Transfer Attributes Select. The CTAS field selects which DSPI_CTARn register is used to set the transfer
attributes for the associated SPI frame. The field is only used in SPI master mode. In SPI slave mode, DSPI_CTAR0
is used. The table below shows how the CTAS values map to the DSPI_CTARn registers.
CTAS
000
001
010
011
Use Clock and Transfer
Attributes from
DSPI_CTAR0
DSPI_CTAR1
DSPI_CTAR2
DSPI_CTAR3
CTAS
100
101
110
111
Use Clock and Transfer
Attributes from
DSPI_CTAR4
DSPI_CTAR5
DSPI_CTAR6
DSPI_CTAR7
EOQ
End Of Queue. The EOQ bit provides a means for host software to signal to the DSPI that the current SPI transfer
is the last in a queue. At the end of the transfer the EOQF bit in the DSPI_SR is set.
0 The SPI data is not the last data to transfer.
1 The SPI data is the last data to transfer.
CTCNT
Clear SPI_TCNT. The CTCNT provides a means for host software to clear the SPI transfer counter. The CTCNT bit
clears the SPI_TCNT field in the DSPI_TCR register. The SPI_TCNT field is cleared before transmission of the
current SPI frame begins.
0 Do not clear SPI_TCNT field in the DSPI_TCR.
1 Clear SPI_TCNT field in the DSPI_TCR.
30-20
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor