PXN20RM Datasheet, PDF (126/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Clock Description
ipg_clk_enable
HLTn
HLTACKn
halt
Halt
control
ipg_clk
halt _{ipg_stop}
Core
Logic
&
ipg_stop_ack
&
Idle
ips_module_en
MDIS
DOZE
ipg_clk
ipg_clk_s
Bus interface
(Memory mapped registers)
halt
ipg_clk
Always clocked logic
<other>_clk
(e.g., osc_clk)
halt
Clock gate
Protocol interface
(e.g., CAN, FlexRay, etc.)
Figure 5-3. Detailed Clock Gating Scheme
5.3 Clock Dividers
(Tied V_SS)
5.3.1 System Clock Select
The source for the system clock can be selected by the SYSCLKSEL field of the SIU system clock register
(SIU_SYSCLK) to be the 16 MHz IRC, the 4 – 40 MHz XTAL, or the FMPLL.
5.3.2 System Clock Dividers
The system clock dividers can be programmed to create a system clock, which is created from the selected
clock source divided by 1, 2, 4, 8, or 16, based on the setting of the SYSCLKDIV field in the SIU system
clock register (SIU_SYSCLK).
5.3.3 External Bus Clock (CLKOUT) Divider
The system clock divided by 1, 2, 4, or 8 based on the settings of the ECDF bit field in the SIU external
clock control register (SIU_ECCR). The reset value of ECDF selects a CLKOUT frequency of one half of
the system clock frequency.
PXN20 Microcontroller Reference Manual, Rev. 1
5-8
Freescale Semiconductor