PXN20RM Datasheet, PDF (445/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Protection Unit (MPU)
Table 18-2. MPU Memory Map (continued)
Offset from
MPU_BASE
(0xFFF1_4000)
Register
0x080C
MPU_RGDAAC3—MPU RGD alternate access control 3
0x0810
MPU_RGDAAC4—MPU RGD alternate access control 4
0x0814
MPU_RGDAAC5—MPU RGD alternate access control 5
0x0818
MPU_RGDAAC6—MPU RGD alternate access control 6
0x081C
MPU_RGDAAC7—MPU RGD alternate access control 7
0x0820
MPU_RGDAAC8—MPU RGD alternate access control 8
0x0824
MPU_RGDAAC9—MPU RGD alternate access control 9
0x0828
MPU_RGDAAC10—MPU RGD alternate access control 10
0x082C
MPU_RGDAAC11—MPU RGD alternate access control 11
0x0830
MPU_RGDAAC12—MPU RGD alternate access control 12
0x0834
MPU_RGDAAC13—MPU RGD alternate access control 13
0x0838
MPU_RGDAAC14—MPU RGD alternate access control 14
0x083C
MPU_RGDAAC15—MPU RGD alternate access control 15
0x0840–0x08FF Reserved
1 _{See register definition.}
Access Reset Value Section/Page
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18.3.2 Register Descriptions
This section lists the MPU registers in address order and describes the registers and their bit fields.
18.3.2.1 MPU Control/Error Status Register (MPU_CESR)
The MPU_CESR provides one byte of error status and three bytes of configuration information. A global
MPU enable/disable bit is also included in this register.
Offset: MPU_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MPERR¹
W
1
0
0
0
HRL
Reset 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
NSP
W
NRGD
0
0
0
0
0
0
0
VLD
Reset 0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Figure 18-3. MPU Control/Error Status Register (MPU_CESR)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
18-5