PXN20RM Datasheet, PDF (801/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Table 27-24. MLB Interrupts
Interrupt Name
MLB Logical Channel 4 Interrupt
MLB Logical Channel 5 Interrupt
MLB Logical Channel 6 Interrupt
MLB Logical Channel 7 Interrupt
MLB Logical Channel 8 Interrupt
MLB Logical Channel 9 Interrupt
MLB Logical Channel 10 Interrupt
MLB Logical Channel 11 Interrupt
MLB Logical Channel 12 Interrupt
MLB Logical Channel 13 Interrupt
MLB Logical Channel 14 Interrupt
MLB Logical Channel 15 Interrupt
PXN20
Interrupt Vector
Interrupt Flag Bits
Interrupt Mask Bits
101
CSCR4[20:31]
CECR4[9:15]
102
CSCR5[20:31]
CECR5[9:15]
103
CSCR6[20:31]
CECR6[9:15]
104
CSCR7[20:31]
CECR7[9:15]
105
CSCR8[20:31]
CECR8[9:15]
106
CSCR9[20:31]
CECR9[9:15]
107
CSCR10[20:31]
CECR10[9:15]
108
CSCR11[20:31]
CECR11[9:15]
109
CSCR12[20:31]
CECR12[9:15]
110
CSCR13[20:31]
CECR13[9:15]
111
CSCR14[20:31]
CECR14[9:15]
112
CSCR15[20:31]
CECR15[9:15]
27.4.3 System Memory Buffers
System software must define system memory buffers for each hardware channel, using the CCBCRn and
CNBCRn registers. Each system memory buffer can occupy as much as 64 KB and must be aligned on a
64 KB boundary; however, the system memory buffers are not required to be contiguous with each other.
Each of the system memory buffers can be configured for either multi-packet or single-packet buffering.
Multi-packet buffering allows the system to reduce the interrupt load at the expense of larger system
memory buffers. Single-packet buffering allows system memory buffer size to be reduced at the expense
of increasing the interrupt rate.
System memory must accommodate situations in which the end of the buffer does not coincide with the
end of the current packet (e.g. asynchronous and control RX packets). This requires the system memory
buffers to allow overflow by the worst-case packet length.
System memory buffers are referred to as Previous Buffer, Current Buffer, and Next Buffer. The Current
Buffer is the system memory buffer the DMA Controller is currently processing and is defined by the
CCBCRn register. The status of the Current Buffer is reflected in CSCRn[STS[3:0]]. The Previous Buffer
is the system memory buffer the DMA Controller completed processing prior to the Current Buffer. The
status of the Previous Buffer is reflected in CSCRn[STS[11:8]]. The Next Buffer is the system memory
buffer the DMA Controller begins processing after the Current Buffer. The Next Buffer is defined by the
CNBCRn register.
For Isochronous RX channels, the DMA Controller aligns incoming packets on a packet boundary in
system memory, dependent on the setting of CECRn[IPL[7:0]] and the arrival of the IsoSyncByte
command.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
27-29