PXN20RM Datasheet, PDF (1187/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Nexus Reg: 0xA
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Read/Write Data
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-19. Read/Write Access Data Register (RWD)
Table 36-25 shows the proper placement of data into the RWD. The “X” in the RWD column indicate byte
lanes with valid data.
Table 36-25. RWD Data Placement for Transfers
Transfer Size and byte offset
RWA[2:0
Byte
xxx
Half Word
xx0
Word
x00
Double Word
000
first RWD pass (low order data)
second RWD pass (high order data)
RWD
RWCS[SZ]
31:24 23:16 15:8 7:0
000
—
—
—
X
001
—
—
X
X
010
X
X
X
X
011
X
X
X
X
X
X
X
X
Table 36-26 shows the mapping of RWD bytes to byte lanes of the AHB read and write data buses.
Table 36-26. RWD data placement for Transfers
Transfer Size and
byte offset
Byte @000
Byte @001
Byte @010
Byte @011
Byte @100
Byte @101
Byte @110
Byte @111
Half@000
Half@010
Half@100
Half@110
Word@000
RWA[2:0]
000
001
010
011
100
101
110
111
000
010
100
110
000
31:24
—
—
—
—
—
—
—
—
—
—
—
—
AHB[31:24]
RWD
23:16
15:8
—
—
—
—
—
—
—
—
—
—
—
—
AHB[23:16]
—
—
—
—
—
—
—
—
AHB[15:8]
AHB[31:24]
AHB[[47:40]
AHB[63:56]
AHB[15:8]
7:0
AHB[7:0]
AHB[15:8]
AHB[23:16]
AHB[31:24]
AHB[39:32]
AHB[[47:40]
AHB[55:48]
AHB[63:56]
AHB[7:0]
AHB[23:16]
AHB[39:32]
AHB[55:48]
AHB[7:0]
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-37