PXN20RM Datasheet, PDF (458/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Protection Unit (MPU)
Typically the appropriate number of region descriptors (MPU_RGDn) are loaded at system startup,
including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the
module. This approach allows all the loaded region descriptors to be enabled simultaneously. If a memory
reference does not hit in any region descriptor, the attempted access is terminated with an error.
18.6 Application Information
In an application’s system, interfacing with the MPU can generally be classified into the following
activities:
1. Creation of a new memory region requires loading the appropriate region descriptor into an
available register location. When a new descriptor is loaded into a RGDn, it would typically be
performed using four 32-bit word writes. As discussed in Section 18.3.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed by clearing
MPU_RGDn.Word3[VLD].
2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAACn) would typically be performed.
Writes to the region descriptor using this alternate access control location do not affect the valid
bit, so there are, by definition, no coherency issues involved with the update. The access rights
associated with the memory region switch instantaneously to the new value as the IPS write
completes.
3. If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses respectively and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.
4. Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
5. When the MPU detects an access error, the current AHB bus cycle is terminated with an error
response and information on the faulting reference captured in the MPU_EARn and MPU_EDRn
registers. The error-terminated AHB bus cycle typically initiates some type of error response in the
originating bus master. For example, a processor core may respond with a bus error exception,
while a data movement bus master may respond with an error interrupt. In any event, the processor
can retrieve the captured error address and detail information simply be reading the
MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is
signaled by MPU_CESR[MPERR].
6. The process identifier seen by the MPU for master ID 0 (z6) is fixed at a value of 0. Regardless of
the actual value loaded into the z6 PID0 register, the MPU always uses a value of 0 when making
the optional process identifier region hit determination. This must be taken into account when
configuring the associated MPU_RGDn.Word3[PID] and MPU.RGDn.Word3[PIDMASK]
descriptor fields.
18-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor