PXN20RM Datasheet, PDF (260/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Boot Assist Module (BAM)
Table 9-3. MMU Configuration for an Internal Boot
TLB
Entr
y
2
Region
reserved¹
Logical Base
Address
0x2000_0000
Physical Base
Address
0x2000_0000
Size
256 MB
3
SRAM
0x4000_0000
0x4000_0000
256 KB
1 _{The MMU can be programmed at this address range, but nothing responds to an access.}
Attributes
Cache enabled
Not guarded
Big Endian
Global PID
Cache inhibited
Not guarded
Big Endian
Global PID
Code type attributes for TLB entries 1–3 are set according to the coding of the user application (VLE or
classic Power Book E).
After configuring the MMU, the BAM determines the selected boot mode and provides the following
features for each of the boot modes:
9.3.3.1 Internal-Boot Mode
When the core determines that internal-boot mode has been selected, a machine check exception is
configured to handle possible ECC read errors that may occur while searching the internal flash to find the
reset configuration halfword (RCHW).
9.3.3.1.1 Reset Configuration Halfword Read
The BAM searches the internal flash memory for a valid RCHW. A valid RCHW is a 16-bit value that
contains a fixed 8-bit boot identifier and some configuration bits. The RCHW is expected to be the first
halfword in one of the low-address space small flash blocks.
The memory addresses of the six locations searched for a valid RCHW are shown in Table 9-4.
Table 9-4. LAS Block Memory Addresses
Block
0
1
4
7
8
9
Address
0x0000_0000
0x0000_4000
0x0001_0000
0x0001_C000
0x0002_0000
0x0003_0000
The BOOT_BLOCK_ADDRESS used in the register descriptions below is the address in Table 9-5 where
the BAM finds a valid RCHW.
PXN20 Microcontroller Reference Manual, Rev. 1
9-6
Freescale Semiconductor