PXN20RM Datasheet, PDF (344/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
Table 12-11. PFCRP0 and PFCRP1 Field Descriptions
Field
Description
LBCFG[3:0]
Line Buffer Configuration. Controls the configuration of the four line buffers in the PFLASH controller. The buffers
can be organized as a pool of available resources or with a fixed partition between instruction and data buffers.
In all cases, when a buffer miss occurs, it is allocated to the least recently used buffer within the group and the
just-fetched entry then marked as most recently used. If the flash access is for the next sequential line, the buffer
is not marked as most recently used until the given address produces a buffer hit.
For PFCRP0, this field is set to 0b0000 by hardware reset. For PFCRP1, this field is set to 0b0011 by hardware
reset.
xx00 All four buffers are available for any flash access, i.e., there is no partitioning of the buffers based on the
access type.
xx01 Reserved.
xx10 The buffers are partitioned into two groups: buffers 0 and 1 allocated for instruction fetches and buffers 2
and 3 for data accesses.
xx11 The buffers are partitioned into two groups: buffers 0,1, 2 allocated for instruction fetches and buffer 3 for
data accesses.
ARB
Arbitration Mode. This field controls which arbitration mode is used. In both fixed priority or round-robin modes,
write requests are prioritized higher than read requests, and read requests are prioritized higher than speculative
prefetch requests whenever both ports issue concurrent requests. This bit is set to 1 by hardware reset.
0 Fixed-priority arbitration is used; the port specified in PRI has highest fixed priority.
1 Round-robin arbitration is used.
Note: This bit is only available in PFCRP0. For PFCRP1, treat this bit as reserved with a reset value of 0.
PRI
Fixed Priority. Controls which port has highest fixed priority when fixed priority arbitration is selected. This field
has no effect when operating in round-robin mode. This bit is cleared by hardware reset.
0 Port p0 is given highest fixed priority.
1 Port p1 is given highest fixed priority.
Note: This bit is only available in PFCRP0. For PFCRP1, treat this bit as reserved with a reset value of 0.
MnPFE
n = 0:2, 4:6
Master n Prefetch Enable. Used to control whether prefetching may be triggered based on the AHB hmaster
attribute. For example, M0PFE enables prefetching for accesses where hmaster[3:0] = 0b0000. Likewise,
M4PFE enables prefetching only when hmaster[3:0] == 0b0100. Note that hmaster[3] is ignored when
determining which MnPFE to use for a given access. These bits are cleared by hardware reset.
0 No prefetching may be triggered by this master.
1 Prefetching may be triggered by this master.
Note: These bits refer to the master ID, not the AMBA port number, as shown in the following:
Master ID
0
1
2
3
4
5
6
7
8
Master Name
Z6 Core
Z0 Core
eDMA
– reserved –
FEC
MLB
FlexRay
– reserved –
Z6 Nexus
12-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor