PXN20RM Datasheet, PDF (231/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
8.3.2.29 Parallel GPIO Pin Data Output Register 2 (SIU_PGPDO2)
The SIU_PGPDO2 register contains the Parallel GPIO Pin Data Output for PE[0:15] and PF[0:15].
Reads and writes to this register are coherent with the registers SIU_GPDO64_67, SIU_GPDO68_71,
SIU_GPDO72_75, SIU_GPDO76_79, SIU_GPDO80_83, SIU_GPDO84_87, SIU_GPDO88_91, and
SIU_GPDO92_95.
Offset SIU_BASE + 0x0C08
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PE0:PE15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PF0:PF15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-37. Parallel GPIO Pin Data Output Register 2 (SIU_PGPDO2)
8.3.2.30 Parallel GPIO Pin Data Output Register 3 (SIU_PGPDO3)
The SIU_PGPDO3 register contains the parallel GPIO pin data output for PG[0:15]and PH[0:15].
Reads and writes to this register are coherent with the registers SIU_GPDO96_99, SIU_GPDO100_103,
SIU_GPDO104_107, SIU_GPDO108_111, SIU_GPDO112_115, SIU_GPDO116_119,
SIU_GPDO120_123, and SIU_GPDO124_127.
Offset: SIU_BASE + 0x0C0C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PG0:PG15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PH0:PH15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-38. Parallel GPIO Pin Data Output Register 3 (SIU_PGPDO3)
8.3.2.31 Parallel GPIO Pin Data Output Register 4 (SIU_PGPDO4)
The SIU_PGPDO4 register contains the parallel GPIO pin data output for PJ[0:15] and PK[0:10].
Reads and writes to this register are coherent with the registers SIU_GPDO18_131, SIU_GPDO132_135,
SIU_GPDO136_139, SIU_GPDO140_143, SIU_GPDO144_147, and SIU_GPDO148_151, and
SIU_GPDO152_154.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-49