PXN20RM Datasheet, PDF (304/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
10.4.3 Details on Handshaking with Processor
10.4.3.1 Software Vector Mode Handshaking
10.4.3.1.1 Acknowledging Interrupt Request to Processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along
with the handshake near the end of the interrupt exception handler, is shown in Figure 10-20. The INTC
examines the peripheral and software settable interrupt requests. When it finds an asserted peripheral or
software settable interrupt request with a higher priority than PRI in the associated INTC current priority
register (INTC_CPR_PRC0 or INTC_CPR_PRC1), it asserts the interrupt request to the associated
processor. The INTVEC field in the associated INTC current priority register (INTC_IACKR_PRC0 or
INTC_IACKR_PRC1) is updated with the preempting interrupt request’s vector when the interrupt request
to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request
to the processor is asserted. The handshaking process is described in Section 10.1.3.1, Software Vector
Mode.
10.4.3.1.2 End of Interrupt Exception Handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR_PRC0 or
INTC_EOIR_PRC1) must be written. When written, the associated LIFO is popped so the preempted
priority is restored into PRI of the associated INTC_CPR_PRC0 or INTC_CPR_PRC1. Before it is
written, the peripheral or software settable flag bit must be cleared so that the peripheral or software
settable interrupt request is negated.
NOTE
To ensure proper operation across all Power Architecture MCUs, execute an
mbar or msync instruction between the access to clear the flag bit and the
write to the INTC_EOIR_PRCn.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request may no longer be asserted. When PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1
is lowered to the priority of the preempted ISR, the interrupt request for the preempted ISR or other
asserted peripherals or software settable interrupt requests at or below that priority will not cause a
preemption. Instead, after the restoration of the preempted context, the processor returns to the next
instruction address it was about to execute before it was preempted. This next instruction is part of the
preempted ISR or the interrupt exception handler’s prolog or epilog.
10-36
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor