PXN20RM Datasheet, PDF (156/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Clocks, Reset, and Power (CRP)
The corresponding CRP_PSCR[PWKSRCF] flag bit is set when a selected and enabled event occurs on
an external pin wakeup source. An interrupt request can be generated for an external pin wakeup by setting
the corresponding CRP_PSCR[PWKSRIE] bit. This interrupt request is pending once the device recovers
from the previous low-power mode.
On exiting sleep mode, the PC value is loaded with the value contained in the CRP_Z6VEC or
CRP_Z0VEC registers. The RECPTR register is a general purpose register which retains a value during
sleep mode and thus may be used by software to hold a generic value used by recovery routines.
A block diagram for the external pin wakeup logic is given in Figure 6-18.
CRP_PWKEN
[PWKENn]
2
To Wakeup Logic
Edge
detect
32
logic
CRP_PWKSRCF
[PWKSRCFn]
To
interrupt
controller
16 MHz IRC
1
128 kHz IRC
0
CRP_PSCR
[WKCLKSEL]
CRP_PWKSRCIE
[PWKSRIEn]
Figure 6-18. External Pin Wakeup Logic
6.3.5.1 Low Power Mode Debug Support
The CRP supports debug after exit from sleep mode for both Nexus and JTAG debug tools. This function
is enabled by setting the NPC PCR[LP_DBG_EN] bit prior to entry into sleep modes.
On entry into sleep mode, if the NPC PCR[LP_DBG_EN] bit is set, the CRP sets the NPC
PCR[SLEEP_SYNC] bit to inform the debug tool that sleep mode is being entered. The CRP waits for this
bit to be cleared before proceeding into sleep mode. During sleep mode, most of the SOC is powered down,
and the contents of the debug registers are lost. The CRP supports restoration of the debug registers on
wakeup from sleep mode. The CRP latches the NPC PCR[LP_DBG_EN] bit when sleep mode is entered.
On wakeup from sleep mode, if the latched bit is set, the CRP places both the Z0 and Z6 cores into debug
mode. The CRP selects the 16 MHz IRC to clock the core debug logic, so the development tool does not
need to drive a clock on the TCK pin at this point. Once both cores have acknowledged that they have
entered debug mode, the CRP allows the TCK pin to drive the debug logic, enables the JTAG pins, and
drives the assertion of the TDO pin.
6-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor