PXN20RM Datasheet, PDF (1164/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
in a manner that allows the individual modules to share the ports, while appearing to the development tool
as a single module.
36.5.2 NPC Features
The NPC performs the following functions:
• Controls arbitration for ownership of the Nexus auxiliary output port
• Nexus device identification register and messaging
• Generates MCKO enable and frequency division control signals
• Controls sharing of EVTO
36.5.3 Control of the device-wide debug mode NPC Memory Map
Table 36-7 shows the NPC registers by index values. The registers are not memory-mapped and can only
be accessed via the TAP. The NPC does not implement the client select control register because the value
does not matter when accessing the registers. Note that the bypass register (refer to Section 36.5.4.1,
Bypass Register) and instruction register (refer to Section 36.5.4.2, Instruction Register) have no index
values. These registers are not accessed in the same manner as Nexus client registers.
Table 36-7. NPC Memory Map
Index
Register Name
Register Description
Size (bits)
0
DID
127
PCR
Device ID register
32
Port configuration register
32
36.5.4 NPC Register Descriptions
This section consists of NPC register descriptions.
36.5.4.1 Bypass Register
The bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDO
when the BYPASS instruction or any unimplemented instructions are active. After entry into the
CAPTURE-DR state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after
selecting the bypass register is always a logic 0.
36.5.4.2 Instruction Register
The NPC uses a 4-bit instruction register as shown in Figure 36-5. The instruction register is accessed via
the SELECT_IR_SCAN path of the tap controller state machine, and allows instructions to be loaded into
the module to enable the NPC for register access (NEXUS_ENABLE) or select the bypass register as the
shift path from TDI to TDO (BYPASS or unimplemented instructions).
Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state, and latched on the
falling edge of TCK in the Update-IR state. The latched instruction value can only be changed in the
Update-IR and test-logic-reset TAP controller states. Synchronous entry into the test-logic-reset state
36-14
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor