PXN20RM Datasheet, PDF (776/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Signal
MLBCLK
MLBSIG
MLBDAT
Port
PK0
PK1
PK2
Table 27-3. Signal Properties
SIU_PCR Register
Function
I/O Reset
SIU_PCR144 MLB Clock
I0
SIU_PCR145 MLB Signal (control/status) I/O 0
SIU_PCR146 MLB Data
I/O 0
Pull
Down
Down
Down
Detailed signal descriptions for the MLB peripheral can be found in Table 27-4.
:
Table 27-4. MLB—Detailed Signal Descriptions
Signal
MLBCLK
MLBDAT
MLBSIG
I/O
Description
I MLB Clock.
State Meaning Asserted/Negated—Supports a 256Fs, 512Fs or 1024Fs clock input from the MLB
controller.
Timing
Assertion/Negation—Supports maximum frequency of 49.2 MHz with a 48 kHz sample
rate.
I/O MLB Data
State Meaning Asserted/Negated—MLB data for serial receive/transmit channel data.
Timing
Assertion/Negation—Input registered on the falling edge of MLBCLK. Output driven
from the rising edge of MLBCLK.
I/O MLB Signal (control/status)
State Meaning Asserted/Negated—MLB signal information for serial transmit channel commands,
serial receive channel responses, and logical channel address information.
Timing
Assertion/Negation—Input registered on the falling edge of MLBCLK. Output driven
from the rising edge of MLBCLK.
27.3 Memory Map and Register Description
27.3.1 Memory Map
Table 27-5 shows the MLB configuration registers. Table 27-6 shows the channel configuration registers
for each channel within the MLB. Table 27-7 shows the overall memory map for the MLB.
Table 27-5. Configuration Registers
Offset from
MLB_BASE
(0xC3F8_4000)
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
Name
DCCR—Device Control Configuration Register
SSCR—System Status Configuration Register
SDCR—System Data Configuration Register
SMCR—System Mask Configuration Register
Access
R/W
R/W
R
R/W
27-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor