PXN20RM Datasheet, PDF (380/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
TLB_entry[V]
TLB_entry[TS]
AS (from MSR[IS] or MSR[DS])
Process ID
TLB_entry[TID]
=?
=? ^{private page}
=0? ^{shared page}
TLB entry Hit
TLB_entry[EPN]
EA page number bits
=?
Figure 13-4. Virtual Address and TLB-Entry Compare Process
13.3.1.3 Effective to Real Address Translation
Instruction accesses are generated by sequential instruction fetches or due to a change in program flow
(branches and interrupts). Data accesses are generated by load, store, and cache management instructions.
The instruction fetch, branch, and load/store units generate 32-bit effective addresses. The MMU translates
this effective address to a 32-bit real address which is then used for memory accesses. Figure 13-5 shows
the effective to real address translation flow.
MSR[DS] for data access
MSR[IS] for instruction fetch
32-bit effective address
NOTE: n = 32–log₂ (page size)
n  20
n = 20 for 4 KB page size
AS PID
0
Effective page address
Virtual Address
TLB
multiple-entry
RPN field of matching entry
Offset
n–1 n
31
Real page number
Offset
0
n–1 n
31
32-bit real address
Figure 13-5. Effective to Real Address Translation Flow
13.3.1.4 Permissions
The application software can restrict access to virtual pages by selectively granting permissions for user
mode read, write, and execute, and supervisor mode read, write, and execute on a per-page basis. For
13-16
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor