PXN20RM Datasheet, PDF (1094/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Address: ADC_BASE + 0x001C
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC
CH95 CH94 CH93 CH92 CH91 CH90 CH89 CH88 CH87 CH86 CH85 CH84 CH83 CH82 CH81 CH80
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC EOC
CH79 CH78 CH77 CH76 CH75 CH74 CH73 CH72 CH71 CH70 CH69 CH68 CH67 CH66 CH65 CH64
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-7. Channel Pending Register 2 (CEOCFR2)
Table 34-7. CEOCFR2 Field Descriptions
Field
EOCCHn
Description
When set, the conversion of channel n has been completed.
34.3.2.7 Interrupt Mask Register (IMR)
The IMR register contains the interrupt enable bits for the ADC.
Address: ADC_BASE + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
W
Reset 1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
W
0
0
0
0
0
0
0
0
MSK
OFF
CANC
OVR
MSKE
OFF
SET
MSK
EOCTU
MSK
JEOC
MSK
JECH
MSK
EOC
MSK
ECH
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-8. Interrupt Mask Register (IMR)
Table 34-8. IMR Field Descriptions
Field
Description
MSKOFFCAN Mask bit for Offset Cancellation Phase Over interrupt (OFFCANCOVR). When set, the OFFCANCOVR
COVR
interrupt is enabled.
MSKEOFFSET Mask bit for Error in Offset Refresh interrupt (EOFFSET). When set, the EOFFSET interrupt is enabled.
34-14
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor