PXN20RM Datasheet, PDF (1218/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Table 36-39. Direct Branch Message Example (12 MDO / 2 MSEO) (continued)
Clock
MDO[11:0]
11 10 9 8 7 6 5 4 3 2 1 0
2 0 0 0 0 0 0 0 0 0 0 I3 I2
3 X X X X S1 S0 T5 T4 T3 T2 T1 T0
MSEO[1:0]
State
1
1 End Packet/End Message
0
0 Start of Next Message
Table 36-40 is an example data write message with 12 MDO / 2 MSEO configuration
Note that T0, A0, D0 are the least significant bits where:
• Tx = TCODE number (fixed)
• Sx = Source processor (fixed)
• Zx = Data size (fixed)
• Ax = Unique portion of the address (variable)
• Dx = Write data (variable - 8, 16 or 32-bit)
Table 36-40. Direct Write Message Example (12 MDO / 2 MSEO)
Clock
0
1
2
3
MDO[11:0]
11 10 9 8 7 6 5 4 3 2 1 0
XXXXXXXXXXXX
Z1 Z0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0
0 0 0 0 0 0 0 A3 A2 A1 A0 Z2
X X X X D7 D6 D5 D4 D3 D2 D1 D0
MSEO[1:0]
1
1
0
0
0
1
1
1
State
Idle (or end of last message)
Start Message
End Packet
End Packet/End Message
36.6.10.8 IEEE 1149.1 (JTAG) RD/WR Sequences
This section contains example JTAG/OnCE sequences used to access resources.
36.6.10.8.1 JTAG Sequence for Accessing Internal Nexus Registers
Table 36-41. Accessing Internal Nexus3 Registers via JTAG/OnCE
Step #
1
2
3
4
5
6
7
8
TMS Pin
1
0
0
0
1
1
1
0
Description
IDLE  SELECT-DR_SCAN
SELECT-DR_SCAN  CAPTURE-DR (Nexus command register value loaded in shifter)
CAPTURE-DR  SHIFT-DR
(7) TCK clocks issued to shift in direction (rd/wr) bit and first 6 bits of Nexus reg. addr.
SHIFT-DR  EXIT1-DR (7th bit of Nexus reg. shifted in)
EXIT1-DR  UPDATE-DR (Nexus shifter is transferred to Nexus command register)
UPDATE-DR  SELECT-DR_SCAN
SELECT-DR_SCAN  CAPTURE-DR (Register value is transferred to Nexus shifter)
36-68
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor