PXN20RM Datasheet, PDF (449/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Protection Unit (MPU)
Offset: MPU_BASE + 0x400 + (16*n) + 0x0 (MPU_RGDn.Word0)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SRTADDR
W
Reset –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SRTADDR
0
0
0
0
0
W
Reset –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 18-6. MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0)
Table 18-6. MPU_RGDn.Word0 Field Descriptions
Field
Description
SRTADDR Start Address. This field defines the most significant bits of the 0-modulo-32 byte start address of the memory
region.
18.3.2.4.2 MPU Region Descriptor n, Word 1 (MPU_RGDn.Word1)
The second word of the MPU region descriptor defines the 31-modulo-32 byte end address of the memory
region. Writes to this word clear the region descriptor’s valid bit.
Offset: MPU_BASE + 0x400 + (16*n) + 0x4 (MPU_RGDn.Word1)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
ENDADDR
W
Reset –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ENDADDR
1
1
1
1
1
W
Reset –
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
Figure 18-7. MPU Region Descriptor, Word 1 Register (MPU_RGDn.Word1)
Table 18-7. MPU_RGDn.Word1 Field Descriptions
Field
Description
ENDADDR End Address. This field defines the most significant bits of the 31-modulo-32 byte end address of the memory
region. There are no hardware checks to verify that ENDADDR > SRTADDR; the software must properly load these
region descriptor fields.
18.3.2.4.3 MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2)
The third word of the MPU region descriptor defines the access control rights of the memory region. The
access control privileges are dependent on two broad classifications of bus masters. Bus masters 0–3 are
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
18-9