PXN20RM Datasheet, PDF (1006/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Offset: ESCI_BASE + 0x0010
Access: User write-only
(TD = 1)
Byte
0
1
2
3
4
5
6
7
R
1st W
P[1:0]
ID[5:0]
2nd W
LEN
3rd W CSM
CSE
CRC
TD (= 1)
TO (ignored)
4th+ W
DATA
Reset
0
0
0
0
0
0
0
0
Figure 31-10. eSCI LIN TX Register (eSCI_LTR) — TX Frame Generation
Offset: ESCI_BASE + 0x0010
Access: User write-only
(TD = 0)
Byte
0
1
2
3
4
5
6
7
R
1st W
P[1:0]
ID[5:0]
2nd W
LEN
3rd W CSM
CSE
CRC
TD (= 0)
TO[11:8]
4th W
TO[7:0]
Reset
0
0
0
0
0
0
0
0
Figure 31-11. eSCI LIN TX Register (eSCI_LTR) — RX Frame Generation
The content and usage of the eSCI LIN TX Register (eSCI_LTR) depends on the transfer direction of
initiated frame. If the application initiates a TX frame transfer, i.e., the TD bit is set to 1, the content and
usage shown in eSCI LIN TX Register (eSCI_LTR) — TX Frame Generation register (Figure 31-10)
applies. If the application initiates an RX frame, i.e., the TD bit is set to 0, the content and usage shown in
eSCI LIN TX Register (eSCI_LTR) — RX Frame Generation register (Figure 31-11) applies.
The initiation and transmit of a TX frame is described in Section 31.4.6.3, LIN TX Frame Generation. The
initiation and transmit of a RX frame is described in Section 31.4.6.4, LIN RX Frame Generation.
NOTE
When the eSCI module is in LIN mode and transmits or receives a LIN
frame, if the CPU requests Stop Mode, and the Stop Mode is left, a
subsequent triggered LIN RX Frame reception may hang. The module will
never assert the eSCI_IFSR2[RXRDY] and eSCI_IFSR2[TXRDY] flags.
The application should ensure that no LIN transmission is running before it
requests Stop Mode by checking the status of the eSCI_IFSR1[TACT] and
eSCI_IFSR1[RACT] status flags.
31-16
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor