PXN20RM Datasheet, PDF (1072/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Cross Triggering Unit (CTU)
Table 33-1. CTU Memory Map
Offset from
CTU_BASE
0xFFFD_8000
Register
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8
0x00AC
0x00B0
CTU_EVTCFGR25² – Event Configuration Register 25
CTU_EVTCFGR26² – Event Configuration Register 26
CTU_EVTCFGR27² – Event Configuration Register 27
CTU_EVTCFGR28² – Event Configuration Register 28
CTU_EVTCFGR29² – Event Configuration Register 29
CTU_EVTSELR30² – Event Configuration Register 30
CTU_EVTSELR31² – Event Configuration Register 31
CTU_EVTSELR32³ – Event Configuration Register 32
0x00B4–0x3FFF Reserved
1 _{Some bits are read-only.}
2 _{For eMIOS channels 0 – 31.}
3 _{For PIT3.}
Access Reset Value
R/W¹
R/W¹
R/W¹
R/W¹
R/W¹
R/W¹
R/W¹
R/W¹
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Section/Page
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Size
32
32
32
32
32
32
32
32
33.4.1.1 Control Status Register (CTU_CSR)
Offset: CTU_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
0
0
0
0
0
0
0 _TRGI TRGI 0
0
W
EN _w1c
PRESC_CONF
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 33-2. Control Status Register (CTU_CSR)
Table 33-2. CTU_CSR Register Field Descriptions
Bit
Description
TRGIEN Trigger Interrupt Request Enable
0 Trigger interrupt request disabled.
1 Trigger interrupt request enabled. A request is generated if the TRGI flag is set.
TRGI
Trigger Interrupt Flag. This flag is set by hardware when the trigger output request is generated after a valid input
event is detected. It is cleared by software.
0 No trigger output request.
1 Trigger output request generated.
33-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor