PXN20RM Datasheet, PDF (467/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
Table 19-5. ESR Field Descriptions (continued)
Field
Description
PRNCE
Platform RAM Non-Correctable Error. The occurrence of a properly enabled non-correctable RAM error generates
an ECSM ECC interrupt request. The faulting address, attributes, and data in either the 512K or 80K array are also
captured in the PREAR, PRESR, PREMR, PREAT, and PREDR registers. To clear this interrupt flag, write a 1 to
this bit. Writing a 0 has no effect.
0 No reportable non-correctable platform RAM error has been detected.
1 A reportable non-correctable platform RAM error has been detected.
PFNCE
Platform Flash Non-Correctable Error. The occurrence of a properly enabled non-correctable flash error generates
an ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the PFEAR,
PFEMR, PFEAT, and PFEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable non-correctable platform flash error has been detected.
1 A reportable non-correctable platform flash error has been detected.
If both a flash and RAM non-correctable error occur at the same time, the ECSM records the event with
the PR1BC as highest priority, then PF1BC, then, PRNCE, and finally PFNCE. If both a 512 KB and an
80 KB RAM non-correctable error occur at the same time, the ECSM records the event with the 512 KB
array.
19.2.2.4 ECC Error Generation Register (EEGR)
The ECC error generation register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the platform memories with ECC, most notably the platform RAM. This
capability is provided for two purposes:
• It provides a software-controlled mechanism for injecting errors into the platform memories during
data writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
The intent is to generate errors during data write cycles, such that subsequent reads of the corrupted
address locations generate ECC events, either single-bit corrections or double-bit noncorrectable errors
that are terminated with an error response.
See Figure 19-4 and Table 19-6 for the ECC error generation register definition.
Offset: ECSM_BASE_ADDR + 0x004A
Access: User read/write
0
R0
W
Reset 0
1
2
3
4
0
0
FRC1BI FR11BI
0
0
0
0
5
6
7
8
9
0
FRCNCI FR1NCI
PREI
_SEL
0
0
0
0
0
10 11 12 13 14 15
ERRBIT
000000
Figure 19-4. ECC Error Generation (EEGR) Register
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
19-7