PXN20RM Datasheet, PDF (492/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Timer Module (STM)
21.3.2.3 STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) is used to enable and service channel n of the timer.
Offset STM_CCR0: STM_BASE + 0x0010
STM_CCR1: STM_BASE + 0x0020
STM_CCR2: STM_BASE + 0x0030
STM_CCR3: STM_BASE + 0x0040
Access: User read/write
0
1
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15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
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0
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R0
0
0
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0
CEN
W
Reset 0
0
0
0
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0
0
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0
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0
0
Field
CEN
Figure 21-3. STM Channel Status and Control Register (STM_CCRn)
Table 21-4. STM_CCRn Field Descriptions
Channel Enable.
0 The channel is disabled.
1 The channel is enabled.
Description
21.3.2.4 STM Channel Interrupt Register (STM_CIRn)
The STM Channel Interrupt Register (STM_CIRn) is used to enable and service channel n of the timer.
Offset: STM_CIR0: STM_BASE + 0x0014
STM_CIR1: STM_BASE + 0x0024
STM_CIR2: STM_BASE + 0x0034
STM_CIR3: STM_BASE + 0x0044
Access: User read/write
0
1
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R0
0
0
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W
Reset 0
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R0
0
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0
0
CIF
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-4. STM Channel Interrupt Register (STM_CIRn)
21-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor