PXN20RM Datasheet, PDF (958/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
30.4.3 Serial Peripheral Interface (SPI) Configuration
The SPI configuration transfers data serially using a shift register and a selection of programmable transfer
attributes. The DSPI is in SPI configuration when the DCONF field in the DSPI_MCR is 0b00. The SPI
frames can be from 4 to 16 bits long. The data to be transmitted can come from queues stored in RAM
external to the DSPI. Host software or a DMA controller can transfer the SPI data from the queues to a
first-in first-out (FIFO) buffer. The received data is stored in entries in the receive FIFO (RX FIFO) buffer.
Host software or a DMA controller can transfer the received data from the RX FIFO to memory external
to the DSPI. The FIFO buffer operations are described in Section 30.4.3.4, Transmit First-In First-Out (TX
FIFO) Buffering Mechanism, and Section 30.4.3.5, Receive First-In First-Out (RX FIFO) Buffering
Mechanism. The interrupt and DMA request conditions are described in Section 30.4.12, DMA and
Interrupt Conditions.
Figure 30-20 shows an example of how a master DSPI connects to a SPI slave in SPI configuration.
DSPI Master
Shift Register
Baud Rate Generator
SIN
SOUT
SOUT
SIN
SCK
SCK
PCSx
SS
SPI/DSI Slave
Shift Register
Figure 30-20. DSPI Connections for SPI and DSI Transfers
The SPI configuration supports two block-specific modes: master mode and slave mode. The FIFO
operations are similar for the master mode and slave mode. The main difference is that in master mode the
DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO
entry. In slave mode, the DSPI only responds to transfers initiated by a bus master external to the DSPI
and the SPI command field of the TX FIFO entry is ignored.
30.4.3.1 SPI Master Mode
In SPI master mode, the DSPI initiates the serial transfers by controlling the serial communications clock
(SCK) and the peripheral chip select (PCS) signals. The SPI command field in the executing TX FIFO
entry determines which CTAR registers are used to set the transfer attributes and which PCS signal to
assert. The command field also contains various bits that help with queue management and transfer
protocol. See Section 30.3.2.6, DSPI PUSH TX FIFO Register (DSPI_PUSHR), for details on the SPI
command fields. The data field in the executing TX FIFO entry is loaded into the shift register and shifted
out on the serial out (SOUT) pin. In SPI master mode, each SPI frame to be transmitted has a command
associated with it allowing for transfer attribute control on a frame by frame basis.
30.4.3.2 SPI Slave Mode
In SPI slave mode, the DSPI responds to transfers initiated by a SPI bus master. The DSPI does not initiate
transfers. Certain transfer attributes such as clock polarity, clock phase and frame size must be set for
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor