PXN20RM Datasheet, PDF (65/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 2
Memory Map
Introduction
2.1 Introduction
This section describes the PXN20 memory map.
All addresses in the device, including those that are reserved, are identified in Table 2-1. The addresses
represent the physical addresses assigned to each IP block.
Table 2-1. PXN20 System Memory Map
Address
Start
End
Size
(KB)
Region Name
Comments
Unimple- Unimple-
mented on mented on
PXS20
PXS21
Flash (AXBS Port S0 and S1)
0x0000_0000
0x0000_4000
0x0000_8000
0x0000_C000
0x0001_0000
0x0001_4000
0x0001_8000
0x0001_C000
0x0002_0000
0x0003_0000
0x0004_0000
0x0006_0000
0x0008_0000
0x000C_0000
0x0010_0000
0x0014_0000
0x0018_0000
0x001C_0000
0x0020_0000
0x00FF_C000
0x0100_0000
0x0000_3FFF
0x0000_7FFF
0x0000_BFFF
0x0000_FFFF
0x0001_3FFF
0x0001_7FFF
0x0001_BFFF
0x0001_FFFF
0x0002_FFFF
0x0003_FFFF
0x0005_FFFF
0x0007_FFFF
0x000B_FFFF
0x000F_FFFF
0x0013_FFFF
0x0017_FFFF
0x001B_FFFF
0x001F_FFFF
0x00FF_BFFF
0x00FF_FFFF
0x1FFF_FFFF
16
16
16
16
16
16
16
16
64
64
128
128
256
256
256
256
256
256
14,320
16
507,904
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Program/Data Flash
Reserved
Shadow Row
Flash Emulation Mapping
LAS Block L0
LAS Block L1
LAS Block L2
LAS Block L3
LAS Block L4
LAS Block L5
LAS Block L6
LAS Block L7
LAS Block L8
LAS Block L9
MAS Block M0
MAS Block M1
HAS Block H0
HAS Block H1
HAS Block H2
External Bus Interface
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
2-1