PXN20RM Datasheet, PDF (154/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Clocks, Reset, and Power (CRP)
State 16
Figure 6-16
13
- Negate system POR
- Bias resistor off
Mode Transition: SLEEP
RUN
T
14
- Block NPC debug
signals
- dbg clk = 16 MHz_IRC
- Assert core debug
enable
Debug
Enabled?
wait core dbg ack
F
16
- Device exits SLEEP
- Un-latch NPC
debug signals
15
- Negate core debug
enable
- Set dbg clk = TCK
- TDO Pin Low
wait NPC PCR
sleep sync bit set
- Negate TDO Pin
- Clear NPC PCR
Sleep Sync Bit
Go to INIT
(Figure 6-15)
Figure 6-17. SLEEP Mode Transition Diagram (Part 2)
6-22
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor