PXN20RM Datasheet, PDF (360/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
The erase operation is resumed by clearing the MCR[ESUS] bit. The flash continues the erase sequence
from one of a set of predefined points. This can extend the time required for the erase operation.
CAUTION
In an erase-suspended program, programming flash locations in blocks
which were being operated on in the erase may corrupt flash core data.
Step 1
Step 2
User mode read state
Write MCR
ERS = 1
Select blocks
Abort
WRITE
EHV = 0
PEG = 0
Step 3 Erase interlock write
Step 4
Write MCR
ERS = 0
User mode read state
Step 5
EHV = 1
High voltage active
WRITE
ESUS = 1
Read MCR
DONE = 1
Access MCR
DONE = 0
DONE
?
PEG Valid Period
DONE = 1
ESUS = 0
EHV = 1
Erase suspend
Write MCR
EHV = 0
Write MCR
PGM = 1
Step 6 Read MCR
Program, Step 2
Success
PEG = 1
Step 7
Step 8
Step 9
PEG
?
Failure
PEG = 0
Write MCR
EHV = 0
Erase
Yes
more blocks
?
No
Write MCR
Note: ESUS cannot be cleared while
EHV = 0. ESUS and EHV cannot
be changed in a single
write operation.
Go to Step 2
Note: PEG remains valid under this
condition until EHV is set high or
ERS is cleared.
ERS = 0
User mode read state
Figure 12-23. Erase Sequence
12-34
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor