PXN20RM Datasheet, PDF (659/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.5.2.35 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
Base + 0x0048
Write: POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
W
FVAL
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-35. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
This register defines the sync frame acceptance filter value. For details on filtering, see Section 26.6.15,
Sync Frame Filtering.
Table 26-41. SFIDAFVR Field Descriptions
Field
FVAL
Description
Filter Value — This field defines the value for the sync frame acceptance filtering.
26.5.2.36 Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
Base + 0x004A
Write: POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
W
FMSK
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-36. Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
This register defines the sync frame acceptance filter mask. For details on filtering see Section 26.6.15.1,
Sync Frame Acceptance Filtering.
Table 26-42. SFIDAFMR Field Descriptions
Field
FMSK
Description
Filter Mask — This field defines the mask for the sync frame acceptance filtering.
26.5.2.37 Network Management Vector Registers (NMVR0–NMVR5)
Base + 0x004C (NMVR0)
Base + 0x004E (NMVR1)
Base + 0x0050 (NMVR2)
Base + 0x0052 (NMVR3)
Base + 0x0054 (NMVR4)
Base + 0x0056 (NMVR5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
NMVP[15:8]
NMVP[7:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-37. Network Management Vector Registers (NMVR0–NMVR5)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
26-45